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    EEEN311_Fall12_W2

    Published: July 18, 2018

    EEEN 311 - LOGIC CIRCUITS AND MICROPROCESSORS WEEK 2

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    EEEN311_Fall12_W2

    • 1. EEEN 311 Logic Circuits & Microprocessors EEEN 311 Logic Circuits & Microprocessors The x86 Microprocessor [Week 2]
    • 2. OBJECTIVES §Describe the Intel family of microprocessors from 8085 to Pentium®. oIn terms of bus size, physical memory & special features. §Explain the function of the EU (execution unit) and BIU (bus interface unit). §Describe pipelining and how it enables the CPU to work faster. §List the registers of the 8086. §Code simple MOV and ADD instructions. oDescribe the effect of these instructions on their operands. §State the purpose of the code segment, data segment, stack segment, and extra segment. §Explain the difference between a logical address and a physical address. §Describe the "little endian" storage convention of x86 microprocessors. §State the purpose of the stack. §Explain the function of PUSH and POP instructions. §List the bits of the flag register and briefly state the purpose of each bit. §Demonstrate the effect of ADD instructions on the flag register. §List the addressing modes of the 8086 and recognize examples of each mode. §Know how to use flowcharts and pseudocode in program development. OBJECTIVES
    • 3. BRIEF HISTORY OF THE x86 FAMILY evolution from 8080/8085 to 8086 BRIEF HISTORY OF THE x86 FAMILY evolution from 8080/8085 to 8086 §In 1978, Intel Corporation introduced the 16-bit 8086 microprocessor, a major improvement over the previous generation 8080/8085 series. 1.The 8086 capacity of 1 megabyte of memory exceeded the 8080/8085 maximum of 64K bytes of memory. 2.8080/8085 was an 8-bit system, which could work on only 8 bits of data at a time. ØData larger than 8 bits had to be broken into 8-bit pieces to be processed by the CPU. 3.8086 was a pipelined processor, as opposed to the non-pipelined 8080/8085.
    • 4. BRIEF HISTORY OF THE x86 FAMILY evolution from 8080/8085 to 8086 BRIEF HISTORY OF THE x86 FAMILY evolution from 8080/8085 to 8086
    • 5. BRIEF HISTORY OF THE x86 FAMILY evolution from 8080/8085 to 8086 §The 8086 microprocessor has a 16-bit data bus, internally and externally. oAll registers are 16 bits wide, and there is a 16-bit data bus to transfer data in and out of the CPU oThere was resistance to a 16-bit external bus as peripherals were designed around 8-bit processors. oA printed circuit board with a 16-bit data bus also cost more. §As a result, Intel came out with the 8088 version. oIdentical to the 8086, but with an 8-bit external data bus. oIt has the same memory capacity of 1 megabyte. oPicked up by IBM as the microprocessor in designing the PC. §The 8088-based IBM PC was a great success, because IBM & Microsoft made it an open system. oDocumentation and specifications of the hardware and software of the PC were made public. oMaking it possible for many vendors to clone the hardware successfully & spawn a major growth in both hardware and software designs based on the IBM PC. oIn contrast to Apple computer which was a fully closed system. BRIEF HISTORY OF THE x86 FAMILY evolution from 8080/8085 to 8086
    • 6. BRIEF HISTORY OF THE x86 FAMILY 80286, 80386, and 80486 BRIEF HISTORY OF THE x86 FAMILY 80286, 80386, and 80486 §Intel introduced the 80286 in 1982, which IBM picked up for the design of the PC AT. o16-bit internal & external data buses. o24 address lines, for 16mb memory. (224 = 16mb) oVirtual memory for the first time. oVirtual memory is way to fool microprocessor into thinking that it has access to an almost unlimited amount of memory by swapping data between disk storage and RAM. •80286 can operate in one of two modes: oReal mode - a faster 8088/8086 with the same maximum of 1 megabyte of memory. oProtected mode - which allows for 16M of memory. oAlso capable of protecting the operating system & programs from accidental or deliberate destruction by a user.
    • 7. BRIEF HISTORY OF THE x86 FAMILY 80286, 80386, and 80486 §In 1985 Intel introduced 80386 (or 80386DX). o32-bit internally/externally, with a 32-bit address bus. oCapable of handling memory of up to 4 gigabytes. (232) oVirtual memory increased to 64 terabytes. (246) §Later Intel introduced 386SX, internally identical, but with a 16-bit external data bus & 24-bit address bus. oThis makes the 386SX system much cheaper. §Since general-purpose processors could not handle mathematical calculations rapidly, Intel introduced numeric data processing chips. oMath co-processors, such as 8087, 80287, 80387. §On the 80486, in 1989, Intel put a greatly enhanced 80386 & math coprocessor on a single chip. oPlus additional features such as cache memory. oCache memory is static RAM with a very fast access time. §All programs written for the 8088/86 will run on 286, 386, and 486 computers. BRIEF HISTORY OF THE x86 FAMILY 80286, 80386, and 80486
    • 8. Slide14 BRIEF HISTORY OF THE x86 FAMILY 80286, 80386, and 80486
    • 9. BRIEF HISTORY OF THE x86 FAMILY Pentium® & Pentium® Pro BRIEF HISTORY OF THE x86 FAMILY Pentium® & Pentium® Pro §In 1992, Intel released the Pentium®. (not 80586) oA name can be copyrighted, but numbers cannot. §On release, Pentium® had speeds of 60 & 66 MHz. oDesigners utilized over 3 million transistors on the Pentium® chip using submicron fabrication technology. oNew design features made speed twice that of 80486/66. oOver 300 times faster than that of the original 8088. §Pentium® is fully compatible with previous x86 processors but includes several new features. oSeparate 8K cache memory for code and data. o64-bit bus, and a vastly improved floating-point processor.
    • 10. BRIEF HISTORY OF THE x86 FAMILY Pentium® & Pentium® Pro BRIEF HISTORY OF THE x86 FAMILY Pentium® & Pentium® Pro §The Pentium® is packaged in a 273-pin PGA chip oBICMOS technology, combines the speed of bipolar transistors with power efficiency of CMOS technology o64-bit data bus, 32-bit registers & 32-bit address bus. oCapable of addressing 4gb of memory. §In 1995 Intel Pentium® Pro was released—the sixth generation x86. o5.5 million transistors. oDesigned primarily for 32-bit servers & workstations.
    • 11. BRIEF HISTORY OF THE x86 FAMILY Pentium® & Pentium® Pro BRIEF HISTORY OF THE x86 FAMILY Pentium® & Pentium® Pro
    • 12. BRIEF HISTORY OF THE x86 FAMILY Pentium® II BRIEF HISTORY OF THE x86 FAMILY Pentium® II §In 1997 Intel introduced the Pentium® II processor o7.5-million-transistor processor featured MMX (MultiMedia Extension) technology incorporated into the CPU. oFor fast graphics and audio processing. §In 1998 the Pentium® II Xeon was released. oPrimary market is for servers and workstations. §In 1999, Celeron® was released. oLower cost & good performance make it ideal for PCs used to meet educational and home business needs.
    • 13. BRIEF HISTORY OF THE x86 FAMILY Pentium® III BRIEF HISTORY OF THE x86 FAMILY Pentium® III §In 1999 Intel released Pentium® III. o9.5-million-transistor processor. o70 new instructions called SIMD. oEnhance video/audio performance in 3-D imaging, and streaming audio. §In 1999 Intel introduced the Pentium® III Xeon. oDesigned more for servers and business workstations with multiprocessor configurations.
    • 14. BRIEF HISTORY OF THE x86 FAMILY Pentium® 4 BRIEF HISTORY OF THE x86 FAMILY Pentium® 4 §The Pentium® 4 debuted late in 1999. oSpeeds of 1.4 to 1.5 GHz. oSystem bus operates at 400 MHz §Completely new 32-bit architecture, called NetBurst. oDesigned for heavy multimedia processing. oVideo, music, and graphic file manipulation on the Internet. oNew cache and pipelining technology & expansion of the multimedia instruction set make the P4 a high-end media processing microprocessor.
    • 15. BRIEF HISTORY OF THE x86 FAMILY Intel 64 Architecture BRIEF HISTORY OF THE x86 FAMILY Intel 64 Architecture §Intel has selected Itanium® as the new brand name for the first product in its 64-bit family of processors. oFormerly called Merced. §The evolution of microprocessors is increasingly influenced by the evolution of the Internet. oItanium® architecture is designed to meet Internet-driven needs for servers & high-performance workstations. oItanium® will have the ability to execute many instructions simultaneously, plus extremely large memory capabilities.
    • 16. Inside The 8088/86 Inside The 8088/86 §There are two ways to make the CPU process information faster: 1.Increase the working frequency. oUsing technology available, with cost considerations. 2.Change the internal architecture of the CPU. Figure 1-1 Internal Block Diagram of the 8088/86 CPU (Reprinted by permission of Intel Corporation, Copyright Intel Corp.1989)
    • 17. Inside The 8088/86 pipelining Inside The 8088/86 pipelining §8085 could either fetch or execute at any given time. oThe idea of pipelining in its simplest form is to allow the CPU to fetch and execute at the same time. Figure 1-2 Pipelined vs Nonpipelined Execution
    • 18. INSIDE THE 8088/86 pipelining INSIDE THE 8088/86 pipelining §Intel implemented pipelining in 8088/86 by splitting the internal structure of the into two sections: oThe execution unit (EU) and the bus interface unit (BIU). oThese two sections work simultaneously. §The BIU accesses memory and peripherals, while the EU executes instructions previously fetched. oThis works only if the BIU keeps ahead of the EU, so the BIU of the 8088/86 has a buffer, or queue oThe buffer is 4 bytes long in 8088 and 6 bytes in 8086. §8088/86 pipelining has two branches, fetch & execute. oIn more powerful computers, it can have many stages.
    • 19. INSIDE THE 8088/86 pipelining INSIDE THE 8088/86 pipelining §If an instruction takes too long to execute, the queue is filled to capacity and the buses will sit idle. §In some circumstances, the microprocessor must flush out the queue. oWhen a jump instruction is executed, the BIU starts to fetch information from the new location in memory and information fetched previously is discarded. oThe EU must wait until the BIU fetches the new instruction oIn computer science terminology, a branch penalty. oIn a pipelined CPU, too much jumping around reduces the efficiency of a program.
    • 20. INSIDE THE 8088/86registers INSIDE THE 8088/86 registers §In the CPU, registers store information temporarily. oOne or two bytes of data to be processed. oThe address of data. §General-purpose registers in 8088/86 processors can be accessed as either 16-bit or 8-bit registers. oAll other registers can be accessed only as the full 16 bits. §In 8088/86, data types are either 8 or 16 bits. oTo access 12-bit data, for example, a 16-bit register must be used with the highest 4 bits set to 0.
    • 21. INSIDE THE 8088/86registers INSIDE THE 8088/86 registers §The bits of a register are numbered in descending order, as shown: §Some instructions use only specific registers. §The first letter of each register indicates its use. –AX is used for the accumulator. –BX is a base addressing register. –CX is a counter in loop operations. –DX points to data in I/O operations.
    • 22. INSIDE THE 8088/86registers INSIDE THE 8088/86 registers §AX accumulator, BX base addressing register, CX counter in loop operations, DX to point data in I/O operations.
    • 23. INTRODUCTION TO ASSEMBLY PROGRAMMING INTRODUCTION TO ASSEMBLY PROGRAMMING §The CPU can work only in binary, very high speeds. oIt is tedious & slow for humans to deal with 0s & 1s in order to program the computer. §A program of 0s & 1s is called machine language. oEarly computer programmers actually coded programs in machine language. §Eventually, Assembly Languages were developed, which provided mnemonics for machine code. oMnemonic is typically used in computer science and engineering literature to refer to codes & abbreviations that are relatively easy to remember.
    • 24. INTRODUCTION TO ASSEMBLY PROGRAMMING §Assembly language is referred to as a low-level language because it deals directly with the internal structure of the CPU. oAssembly language programs must be translated into machine code by a program called an assembler. oTo program in Assembly language, programmers must know the number of registers and their size. oAs well as other details of the CPU. §Today there are many different programming languages, such as C/C++, BASIC, C#, etc. oCalled high-level languages because the programmer does not have to be concerned with internal CPU details. §High-level languages are translated into machine code by a program called a compiler. oTo write a program in C, one must use a C compiler to translate the program into machine language INTRODUCTION TO ASSEMBLY PROGRAMMING
    • 25. INTRODUCTION TO ASSEMBLY PROGRAMMING §An Assembly language program consists of a series of lines of Assembly language instructions. §An Assembly language instruction consists of a mnemonic, optionally followed by one or two operands. oOperands are the data items being manipulated. oMnemonics are commands to the CPU, telling it what to do with those items. §Two widely used instructions are move & add. INTRODUCTION TO ASSEMBLY PROGRAMMING
    • 26. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction §The MOV instruction copies data from one location to another, using this format: §This instruction tells the CPU to move (in reality, copy) the source operand to the destination operand. –For example, the instruction "MOV DX,CX" copies the contents of register CX to register DX. –After this instruction is executed, register DX will have the same value as register CX. §Instruction does not affect the source operand.
    • 27. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction §This program first loads CL with value 55H, then moves this value around to various registers inside the CPU. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction
    • 28. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction §The use of 16-bit registers is shown here: INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction
    • 29. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction §In the 8086 CPU, data can be moved among all the registers, as long as the source and destination registers match in size (Except the flag register.) oThere is no such instruction as "MOV FR,AX“. §Code such as "MOV AL,DX" will cause an error. oOne cannot move the contents of a 16-bit register into an 8-bit register. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction
    • 30. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction §Using the MOV instruction, data can be moved directly into non-segment registers only. oThe following demonstrates legal & illegal instructions. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction
    • 31. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction §Values cannot be loaded directly into any segment register (CS, DS, ES, or SS). oTo load a value into a segment register, load it to a non-segment register, then move it to the segment register. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction
    • 32. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction §If a value less than FFH is moved into a 16-bit register, the rest of the bits are assumed to be zeros. oFor example, in "MOV BX,5" the result will be BX = 0005. oBH = 00 and BL = 05. §Moving a value that is too large into a register will cause an error. INTRODUCTION TO ASSEMBLY PROGRAMMING MOV instruction
    • 33. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction –Executing the program above results in: AL = 59H (25H + 34H = 59H) and BL = 34H. •The contents of BL do not change. §The ADD instruction has the following format: §ADD tells the CPU to add the source & destination operands and put the result in the destination. –To add two numbers such as 25H and 34H, each can be moved to a register, then added together: INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction
    • 34. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction §The program above can be written in many ways, depending on the registers used, such as: –The program above results in DH = 59H and CL = 34H. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction
    • 35. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction §Is it necessary to move both data items into registers before adding them together? oNo, it is not necessary. –In the case above, while one register contained one value, the second value followed the instruction as an operand. •This is called an immediate operand. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction
    • 36. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction §An 8-bit register can hold numbers up to FFH. oFor numbers larger than FFH (255 decimal), a 16-bit register such as AX, BX, CX, or DX must be used. §The following program can add 34EH & 6A5H: –Running the program gives DX = 9F3H. •(34E + 6A5 = 9F3) and AX = 34E. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction
    • 37. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction §Any 16-bit non-segment registers could have been used to perform the action above: –The general-purpose registers are typically used in arithmetic operations • Register AX is sometimes referred to as the accumulator. INTRODUCTION TO ASSEMBLY PROGRAMMING ADD instruction
    • 38. INTRODUCTION TO PROGRAM SEGMENTS  INTRODUCTION TO PROGRAM SEGMENTS §A typical Assembly language program consists of at least three segments: oA code segment - which contains the Assembly language instructions that perform the tasks that the program was designed to accomplish. oA data segment - used to store information (data) to be processed by the instructions in the code segment. oA stack segment - used by the CPU to store information temporarily.
    • 39. INTRODUCTION TO PROGRAM SEGMENTS origin and definition of the segment INTRODUCTION TO PROGRAM SEGMENTS origin and definition of the segment §A segment is an area of memory that includes up to 64K bytes, and begins on an address evenly divisible by 16 (such an address ends in 0H) o8085 addressed a maximum of 64K of physical memory, since it had only 16 pins for address lines. (216 = 64K) oLimitation was carried into 8088/86 design for compatibility. §In 8085 there was 64K bytes of memory for all code, data, and stack information. oIn 8088/86 there can be up to 64K bytes in each category at any given time. oThe code segment, data segment, and stack segment.
    • 40. INTRODUCTION TO PROGRAM SEGMENTS logical address and physical address INTRODUCTION TO PROGRAM SEGMENTS logical address and physical address §In literature concerning 8086, there are three types of addresses mentioned frequently: oThe physical address - the 20-bit address actually on the address pins of the 8086 processor, decoded by the memory interfacing circuitry. •This address can have a range of 00000H to FFFFFH. •An actual physical location in RAM or ROM within the 1 mb memory range. oThe offset address - a location in a 64K-byte segment range, which can can range from 0000H to FFFFH. oThe logical address - which consists of a segment value and an offset address.
    • 41. INTRODUCTION TO PROGRAM SEGMENTS code segment  INTRODUCTION TO PROGRAM SEGMENTS code segment §To execute a program, 8086 fetches the instructions (opcodes and operands) from the code segment. oThe logical address of an instruction always consists of a CS (code segment) and an IP (instruction pointer), shown in CS:IP format. oThe physical address for the location of the instruction is generated by shifting the CS left one hex digit, then adding it to the IP. •IP contains the offset address. §The resulting 20-bit address is called the physical address since it is put on the external physical address bus pins.
    • 42. INTRODUCTION TO PROGRAM SEGMENTS code segment  INTRODUCTION TO PROGRAM SEGMENTS code segment §Assume values in CS & IP as shown in the diagram: –The offset address contained in IP, is 95F3H. –The logical address is CS:IP, or 2500:95F3H. –The physical address will be 25000 + 95F3 = 2E5F3H
    • 43. INTRODUCTION TO PROGRAM SEGMENTS code segment  §Calculate the physical address of an instruction: –The microprocessor will retrieve the instruction from memory locations starting at 2E5F3. INTRODUCTION TO PROGRAM SEGMENTS code segment
    • 44. INTRODUCTION TO PROGRAM SEGMENTS code segment  §Calculate the physical address of an instruction: –Since IP can have a minimum value of 0000H and a maximum of FFFFH, the logical address range in this example is 2500:0000 to 2500:FFFF. INTRODUCTION TO PROGRAM SEGMENTS code segment
    • 45. INTRODUCTION TO PROGRAM SEGMENTS code segment  –This means that the lowest memory location of the code segment above will be 25000H (25000 + 0000) and the highest memory location will be 34FFFH (25000 + FFFF). §Calculate the physical address of an instruction: INTRODUCTION TO PROGRAM SEGMENTS code segment
    • 46. INTRODUCTION TO PROGRAM SEGMENTS code segment  §What happens if the desired instructions are located beyond these two limits? oThe value of CS must be changed to access those instructions. INTRODUCTION TO PROGRAM SEGMENTS code segment